Multi-Cache Profiling of Parallel Processing Programs Using Simics

This paper presents a multi-cache profiler for shared memory multiprocessor systems. For each program’s static data structure, the profiler outputs the readand write-miss frequencies that are due to cache line migrations. Those program’s static data structures, which their manipulations, result in excessive cache line migrations—potentially a source for excessive falsemisses—are identified. The frequency of line migrations from cache to cache may inherently depend on the algorithm or may depend on the coding. The paper illustrates that our profiled data can be useful for analyzing algorithms and programs from cache performance points of views as well as for code optimizations to reduce cache line migrations. This profiler is created by extending Simics single-cache profiling capabilities. It combines the profiled data from the individual cache memories and the virtual memory addresses assigned to each of the static data structures of a parallel processing program.